1. Field of the Invention
The present invention relates to data processing apparatus having register banks with bit lines for reading the contents of the register bank.
2. Description of the Prior Art
A typical data processing apparatus includes a processor core having a register bank comprising a plurality of registers, the registers being used to store data values used by the processor core.
In a typical register bank, there will be an array of static memory elements or cells, each static memory cell being arranged to store a data bit. An individual register within the register bank typically consists of a plurality of such static memory cells, which are usually arranged in a row. The data bits stored by that row of static memory cells then represent the data value stored by that register. Hence, taking the example of a register bank containing 32 bit registers, each register will consist of 32 static memory cells.
It will be appreciated that the actual data value stored in a register may be an item of data to which the processor core can apply processing instructions, or may indeed be an instruction to be executed by the processor core. Hence, for the purposes of the present application, the term "data value" refers to both data and instructions that may be stored within the registers of the register bank.
To read the data value stored by a register, each register is provided with a word line to which each memory cell forming that register is connected. A read signal is then provided to those memory cells via the word line when it is desired to read the contents of the register.
Further, each memory cell is connected to an associated bit line such that corresponding memory cells in each register are connected to the same bit line, with the memory cells of any particular register being connected to different bit lines. Prior to a register read process taking place, each bit line is typically precharged to a predetermined voltage. Then, when the read signal is provided over the word line of a particular register, each memory cell of that register is arranged to selectively discharge its associated bit line dependent on the value of the data bit stored by that register. The outputs of the bit lines associated with each memory cell of the register then provide an indication of the data value stored by that register.
To improve the processing speed of the processor core, it is desirable to reduce the frequency with which data values have to be moved back and forth between the register bank and cache or main memory. This can be achieved by increasing the number of registers within the register bank, so that more data values can be retained in the register bank.
However, this clearly increases the size of the register bank, and hence increases the length of the bit lines which are connected to corresponding memory cells of the registers in the register bank. This increases the capacitance of the bit line, and hence increases the power that must be consumed by the memory cells in order to discharge those bit lines during a register read operation, and then be used subsequently to precharge the bit lines following the register read.
Generally in the field of data processing, it is desirable to reduce the power consumption wherever possible, since as the power consumption increases, so typically the heat generated by the data processing circuit increases, and this then requires appropriate heat dissipation provisions to be made.
A further consideration is that such data processing apparatus are commonly used in battery-operated devices, such as laptop computers, portable telephones, personal organisers, etc. Clearly in such instances, power consumption is a very important issue, since the operating life of the device (i.e. the time between replacing or recharging the batteries) is increased as the power consumption is reduced, and a device that has an improved operating life over competing devices is generally more attractive to the consumer.
Hence, it is an object of the present invention to provide a data processing apparatus and method which reduces the power consumption associated with charging and discharging bit lines in a register bank.